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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad1857/ad1858 stereo, single supply 16-, 18- and 20-bit sigma-delta dacs functional block diagram one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 product overview the ad1857/ad1858 are complete single-chip stereo digital audio playback components. they each comprise an advanced digital interpolation filter, a revolutionary linearity-compensated multibit sigma-delta ( ?d ) modulator with dither, a jitter-tolerant dac, switched capacitor and continuous time analog filters and analog output drive circuitry. other features include digital de-emphasis processing and mute. the ad1857/ad1858 support continuously variable sample rates with essentially linear phase response, and support 50/15 m s digital de-emphasis intended for redbook 44.1 khz sample frequency playback from compact discs. the user must provide a master clock that is synchronous with the left/right clock at 256 or 384 times the intended sample frequency. the ad1857/ad1858 have a simple but very flexible serial data input port that allows for glueless interconnection to a variety of adcs, dsp chips, aes/ebu receivers and sample rate con- verters. the ad1857 serial data input port can be configured in either 16-bit, 18-bit or 20-bit left-justified or i 2 s-justified modes. the ad1858 serial data input port can be configured in either 16-bit right-justified or dsp serial port compatible modes. the ad1857/ad1858 accept serial audio data in msb first, twos-complement format. a power-down mode is offered to minimize power consumption when the device is inactive. the ad1857/ad1858 operate from a single +5 v power supply. they are fabricated on a single monolithic integrated circuit and housed in 20-pin ssop packages for operation over the temperature range 0 c to +70 c. features low cost, high performance stereo dacs 128 times oversampling interpolation filter multibit sd modulator with triangular pdf dither discrete time and continuous time analog reconstruction filters extremely low out-of-band energy buffered outputs with 2 k v output load drive 94 db dynamic range, C90 db thd+n performance digital de-emphasis and mute 6 0.1 8 c maximum phase linearity deviation continuously variable sample rate support power-down mode 16-, 18- and 20-bit i 2 s-justified, left-justified modes offered on ad1857 accepts 24-bit word 16-bit right-justified and dsp serial port modes offered on ad1858 single +5 v supply 20-pin ssop package applications digital cable tv and direct broadcast satellite set-top decoder boxes video laser disk, video cd and cd-i players high definition televisions, digital audio broadcast receivers cd, cd-r, dat, dcc and md players digital audio workstations, computer multimedia products mute mute multibit sd modulator ad1857/ad1858 analog supply digital supply 16-/18-/20-bit digital data input analog outputs mute clock mode clock in serial mode common mode 2 4 3 de-emphasis power-down / reset 128x interpolation filter serial data interface multibit sd modulator 128x interpolation filter voltage reference analog filter clock circuit output buffer analog filter output buffer dac dac
test conditions unless otherwise noted supply voltages (av dd , dv dd ) +5.0 v ambient temperature 25 c input clock (f mclk ) 11.2896 mhz (256 f s mode) input signal 1.0013 khz C0.5 db full scale input sample rate 44.1 khz measurement bandwidth 20 hz to 20 khz ad1857 input data wordwidth 18 bits ad1858 input data wordwidth 16 bits load capacitance 100 pf load impedance 47 k w input voltage hi (v ih ) 2.4 v input voltage lo (v il ) 0.8 v i 2 s-justified mode (ref. figure 7) for ad1857, right-justified mode (ref. figure 8) for ad1858. performance of the right and left channels are identical (exclusive of the interchannel gain mismatch and interchannel phase de viation specifications). values in bold typeface are tested, all others are guaranteed, not tested. analog performance min typ max units ad1857 resolution 18 bits ad1858 resolution 16 bits dynamic range (20 hz to 20 khz, C60 db input) no a-weight filter 91 db with a-weight filter 94 db total harmonic distortion + noise C90 C85 db 0.003 0.006 % analog outputs single-ended output range ( full scale) 2.8 3.0 3.2 v p-p output impedance at each output pin <200 w output capacitance at each output pin 20 pf out-of-band energy (0.5 f s to 100 khz) C72.5 db cmout 2.1 2.25 2.4 v dc accuracy gain error 3.0 6 7.5 % interchannel gain mismatch 0.01 6 0.2 db gain drift 150 300 ppm/ c interchannel crosstalk (eiaj method) C120 C100 db interchannel phase deviation 0.1 degrees mute attenuation C100 C90 db de-emphasis gain error 0.1 db digital i/o min max units input voltage hi (v ih ) 2.4 v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 2.4 v) 10 m a input leakage (i il @ v il = 0.8 v) 10 m a input capacitance 20 pf rev. 0 C2C ad1857/ad1858Cspecifications
digital timing (guaranteed over 0 c to +70 c, av dd = dv dd = +5.0 v 5%) min max units t dml mclk lo pulse width (256 f s mode) 35 ns t dmh mclk hi pulse width (256 f s mode) 40 ns t dmp mclk period (256 f s mode) 88.577 ns t dml mclk lo pulse width (384 f s mode) 25 ns t dmh mclk hi pulse width (384 f s mode) 25 ns t dmp mclk period (384 f s mode) 59.0514 ns t dbh bclk hi pulse width 20 ns t dbl bclk lo pulse width 20 ns t dbp bclk period 354.308 ns t dls l r clk setup 20 ns t dlh l r clk hold 5 ns t dds sdata setup 5 ns t ddh sdata hold 10 ns t pdrp pd / rst lo pulse width 4 mclk periods ns (355 ns @ 11.2896 mhz) power min typ max units supplies voltage, analog and digital 4.75 5 5.25 v analog current 35 40 ma analog current C power-down 30 60 m a digital current 20 25 ma digital current C power-down 5 11 ma dissipation operation C both supplies 275 325 mw operation C analog supply 175 200 mw operation C digital supply 100 125 mw power-down C both supplies 25 56 mw power supply rejection ratio 1 khz 300 mv p-p signal at analog supply pins C60 db 20 khz 300 mv p-p signal at analog supply pins C50 db temperature range min typ max units specifications guaranteed 25 c functionality guaranteed 0 70 c storage C55 125 c absolute maximum ratings* min typ max units dv dd to dgnd C0.3 6 v av dd to agnd C0.3 6 v digital inputs dgnd C 0.3 dv dd + 0.3 v analog outputs agnd C 0.3 av dd + 0.3 v agnd to dgnd C0.3 0.3 v reference voltage indefinite short circuit to ground soldering +300 c 10 sec *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rev. 0 C3C ad1857/ad1858
ad1857/ad1858 rev. 0 C4C package characteristics min typ max units q ja (thermal resistance [junction-to-ambient]) 195 c/w q jc (thermal resistance [junction-to-case]) 13 c/w digital filter characteristics min max units passband ripple 0.045 db stopband 1 attenuation 62 db 48 khz f s passband 0 21.312 khz stopband 26.688 6117 khz 44.1 khz f s passband 0 19.580 khz stopband 24.520 5620 khz 32 khz f s passband 0 14.208 khz stopband 17.792 4078 khz other f s passband 0 0.444 f s stopband 0.556 127.444 f s group delay 40/f s sec group delay variation 0 m s analog filter characteristics min typ max units passband ripple C0.075 db stopband attenuation (at 64 f s )58db notes 1 stopband nominally repeats itself at multiples of 128 f s , where f s is the input word rate. thus the digital filter will attenuate to 62 db across the frequency spectrum, except for a range 0.55 f s wide at multiples of 128 f s . specifications subject to change without notice. pin configuration ordering guide package package model temperature description option* ad1857jrs 0 c to +70 c 20-lead ssop rs-20 ad1857jrsrl 0 c to +70 c 20-lead ssop rs-20 on 13" reels ad1858jrs 0 c to +70 c 20-lead ssop rs-20 ad1858jrsrl 0 c to +70 c 20-lead ssop rs-20 on 13" reels *rs = shrink small outline warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1857/ad1858 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad1857 ad1858 nc = no connect mclk dv dd l r clk bclk sdata pd / rst mode nc av dd mute dgnd deemp 384/ 256 av dd outl agnd cmout filt agnd outr
ad1857/ad1858 rev. 0 C5C pin list digital audio serial input interfaces pin name number i/o description sdata 20 i serial input, msb first, containing two channels of 16, 18 or 20 bits (ad1857) or 16 bits (ad1858) of twos complement data per channel. bclk 19 i bit clock input for input data. need not run continuously; may be gated or used in a burst fashion. l r clk 18 i left/ right clock input for input data. must run continuously. mode 3 i input serial data port mode control. selects between i 2 s-justified (hi) and left -justified (lo) on the ad1857. selects between dsp serial port style mode ( hi) and right- justified (lo) on the ad1858. the state of the mode pin should be changed only when the ad1857/ad1858 is held in reset ( pd / rst lo). otherwise, the ad1857/ ad1858 serial port may lose synchronism. control and clock signals pin name number i/o description pd / rst 2 i power-down/reset. the ad1857/ad1858 are placed in a low power consumption sleep mode when this pin is held lo. the ad1857/ad1858 are reset on the rising edge of this signal. connect hi for normal operation. deemp 5 i de-emphasis. digital de-emphasis is enabled when this input signal is hi. this is used to impose a 50/15 m s response characteristic on the output audio spectrum at an assumed 44.1 khz sample rate. mute 15 i mute. assert hi to mute both stereo analog outputs of the ad1857/ad1858. deassert lo for normal operation. mclk 1 i master clock input. connect to an external clock source at either 256 or 384 times the intended sample frequency as determined by the 384/ 256 pin. must be synchro- nous with l r clk, but may have any phase with respect to l r clk. 384/ 256 6 i selects the master clock mode as either 384 times the intended sample frequency (hi) or 256 times the intended sample frequency (lo). the state of this input should be hardwired to logic lo or logic hi or may be changed while the ad1857/ ad1858 is in power-down/reset. it must not be changed while the ad1857/ad1858 is operational. analog signals pin name number i/o description filt 11 o voltage reference filter capacitor connection. bypass and decouple the voltage reference with parallel 10 m f and 0.1 m f capacitors to the agnd pin. cmout 10 o voltage reference common mode output. should be decoupled with 10 m f capacitor to the agnd pin or plane. this output is available externally for dc coupling and level-shifting. cmout should not have any signal dependent load, or used where it will sink or source current. outl 8 o left channel line level analog output. outr 13 o right channel line level analog output. power supply connections and miscellaneous pin name number i/o description av dd 7, 14 i analog power supply. connect to analog +5 v supply. agnd 9, 12 i analog ground. dv dd 17 i digital power supply. connect to digital +5 v supply. dgnd 16 i digital ground. n/c 4 no connect. reserved. do not connect.
ad1857/ad1858 rev. 0 C6C definitions dynamic range the ratio of a full-scale output signal to the integrated output noise in the passband (0 khz to 20 khz), expressed in decibels (db). dynamic range is measured with a C60 db input signal and is equal to (s/[thd+n]) + 60 db. note that spurious harmonics are below the noise with a C60 db input, so the noise level establishes the dynamic range. this measurement tech- nique is consistent with the recommendations of the audio engineering society (aes17-1991) and the electronic industries association of japan (eiaj cp-307). total harmonic distortion + noise (thd+n) the ratio of the root-mean-square (rms) value of a full-scale fundamental input signal to the rms sum of all other spectral components in the passband, expressed in decibels (db) and as a percentage. passband the region of the frequency spectrum unaffected by the attenuation of the digital interpolation filter. passband ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the passband, expressed in decibels. stopband the region of the frequency spectrum attenuated by the digital interpolation filter to the degree specified by stopband attenuation. gain error with a near full-scale input, the ratio of actual output to expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. crosstalk (eiaj method) ratio of response on one channel with a zero input, to a full- scale 1 khz sine-wave input on the other channel, expressed in decibels. interchannel phase deviation difference in output sampling times between stereo channels, expressed as a phase difference in degrees between 1 khz inputs. power supply rejection with zero input, signal present at the output when a 300 mv p-p signal is applied to power supply pins, expressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converters output, expressed in seconds(s). more precisely, the derivative of radian phase with respect to radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between the largest and the smallest group delays in passband, expressed in microseconds ( m s). de-emphasis gain error a measure, expressed in decibels, of the difference between the ideal 50/15 m s de-emphasis filter response, and the actual 50/15 m s de-emphasis filter response.
ad1857/ad1858 rev. 0 C7C typical performance characteristics figures 1 through 4 illustrate the typical performance of the ad1857/ad1858 as measured by an audio precision system two. signal-to-noise (dynamic range) thd+n performance is shown under a range of conditions. figure 5 shows the power supply rejection performance of the ad1857/ad1858. the channel separation performance of the ad1857/ad1858 is shown in figure 6. the digital filter transfer function is shown in figure 7. khz dbr a 0 ?00 0 2.5 20.0
ad1857/ad1858 rev. 0 C8C typical performance characteristics (continued) khz dbr a ?0 0 2.5 20.0
ad1857/ad1858 rev. 0 C9C theory of operation the ad1857/ad1858 offer the advantages of sigma-delta con- version architectures (no component trims, low cost cmos process technology, superb low-level linearity performance) with the advantages of conventional multibit r-2r resistive ladder audio dacs (continuously variable sample rate support, jitter tolerance, very low output noise, etc.). the use of a multibit sigma-delta modulator means that the ad1857/ad1858 generate dramatically lower amounts of out- of-band noise energy, which greatly reduces the requirement on post dac filtering. the required post-filtering is integrated on the ad1857/ad1858. the ad1857/ad1858s multibit sigma- delta modulator is also highly immune to digital substrate noise. serial audio data interface the serial audio data interface uses the bit clock (bclk) simply to clock the data into the ad1857/ad1858. the bit clock may therefore be asynchronous to the l/ r clock. the left/ right clock (l r clk) is both a framing signal and the sample frequency input to the interpolation filter. the left/ right clock must be synchronous with mclk, but may have any phase relationship with respect to mclk; l r clk is generally synchronously divided down from mclk. the sdata input carries the serial stereo digital audio in msb first, twos-complement format. digital interpolation filter the purpose of the interpolator is to oversample the input data, i.e., to increase the sample rate so the first signal image is moved out to the oversample frequency, which relaxes the attenuation requirements on the analog reconstruction filter. the ad1857/ad1858 interpolator increases the input data sample rate by 128. the interpolation is performed using a multistage fir digital filter structure. the first stage is a droop equalizer; the second and third stages are halfband filters; and the fourth stage is a second-order comb filter. the fir filter implementation is multiplier-free, i.e., the multiplies are performed using shift-and-add o perations. the fir filter coefficients have been recoded in a canonical sign digit format to enable the use of a compact arithmetic logic unit without a multiplier. multibit sigma-delta modulator the ad1857/ad 1858 employ a 4-bit second-order sigma-delta modulator. whereas a traditional single-bit sigma-delta modulator has two levels of quantization, the ad1857/ad1858s has 17 levels of quantization. traditional single-bit sigma-delta modulators sample the input signal at 64 times the input sample rate; the ad1857/ad1858 sample the input signal at 128 times the input sample rate. the additional quantization levels combined with the high oversampling ratio means that the ad1857/ad1858 dac output spectrum contains dramatically lower levels of out-of-band noise energy, which is a major stumbling block with more traditional single-bit sigma-delta architectures. this means that the post-dac analog reconstruction filter has reduced transition band steepness and attenuation requirements, which directly equates to lower phase distortion. since the analog filtering generally establishes the noise and distortion characteristic of the dac, the reduced requirements translate into better audio performance. multibit sigma-delta modulators bring an additional benefit: they are essentially free of stability (and therefore potential loop oscillation) problems. they are able to scale the output signal to a wider range of the voltage reference, which can increase the overall dynamic range of the converter. the conventional problem limiting the performance of multibit sigma-delta converters is the nonlinearity of the passive circuit elements used to sum the quantization levels. analog devices has developed (and received patents on) a revolutionary architecture that overcomes the circuit element linearity problem that otherwise limits the performance of multibit sigma-delta audio converters. this new architecture provides the ad1857/ad1858 with the same excellent differential nonlinearity and linearity drift (over temperature and time) specifications as single bit sigma-delta dacs. the ad 1857/ad1858s multibit modulator has another important advantage; it has a high immunity to substrate digital noise. substrate noise can be a significant problem in mixed- signal designs, where it can produce intermodulation products that fold down into the audio band. the ad1857/ad1858 are approximately eight times less sensitive to digital substrate noise (voltage reference noise injection) than equivalent single-bit sigma-delta modulator based dacs. dither generator the ad1857/ad1858 include an on-chip dither generator that is intended to further whiten the quantization noise i ntroduced by the multibit dac. the dither has a triangular probability distribution function (pdf) characteristic, which is generally considered to create the most favorable noise shaping of the residual quantization noise. the ad185 7/ad1858 are among the first low cost ic audio d acs to include dithering. analog filtering the ad1857/ad1858 include a second-order switched capacitor discrete time low-pass filter followed by a first-order analog continuous time low-pass filter. these filters eliminate the need for any additional off-chip external reconstruction filtering. this on-chip switched capacitor analog filtering is essential to reduce the deleterious effects of master clock jitter. digital de-emphasis processing the ad1857/ad1858 include digital circuitry for implementing the 50/15 m s de-emphasis frequency response characteristic. a control pin deemp (pin 5) enables de-emphasis when it is asserted hi. the digital de-emphasis response assumes a sample frequency of 44.1 khz. the transfer function magnitude error of this digital filter is less than 0.1 db (from 0 khz to 20 khz) compared to a 50/15 m s continuous time filter. if the sample frequency is not 44.1 khz, the de-emphasis frequency response will scale directly with frequency. the 44.1 khz f s digital de- emphasis frequency response is shown in figure 8. gain ?db 0 ?0 f1 3.183 f2 10.61 t1 = 50? t2 = 15? frequency ?khz figure 8. digital de-emphasis frequency response
ad1857/ad1858 rev. 0 C10C operating features serial data input port the ad1857/ad1858 use the frequency of the left/ right and master input clocks to determine the input sample rate. gen- erally, the master clock (mclk) is divided down to synthesize the left/ right clock (l r clk). l r clk must run continuously and transition twice per stereo sample period (except in the left- justified dsp serial port style mode, when it transitions four times per stereo sample period). the bit clock (bclk) is edge- sensitive and may be used in a gated or burst mode, i.e., a stream of pulses during data transmission followed by periods of inactivity. the bit clock is only used to write the audio data into the serial input port. it is important that the left/ right clock is clean, with monotonic rising and falling edge transitions and no excessive overshoot or undershoot that could cause false clock triggering of the ad1857/ad1858. the ad1857/ad1858s flexible serial data input port accepts data in twos-complement, msb first format. the left channel data field always precedes the right channel data field. the input data consists of 16, 18 or 20 bits (16 bits only to the ad1858). all digital inputs are specified to ttl logic levels. the input data port is configured by a control pin, mode, pin 3. the ad1857 and the ad1858 are identical except for the serial data input port modes offered. the ad1857 offers i 2 s-justified and left-ju stified modes, for 16-, 18- or 20-bit data words. the ad1858 offers right-justified and dsp serial port style mode for 16-bit data words. note: during the first 30,000 mclk cycles after coming out of reset, the ad1857/ad1858 synchronizes its internal sequencer counter to the incoming l r clk. after this period of time, it is assumed that the l r clk and the internal ad1857/ad1858 output channels could be switched (l to r and r to l). theref ore, if the incoming l r clk is stopped and then restarted with a different phase, the ad1857/ad1858 should be reset again to synchronize with this new clock. serial input port modes the ad1857/ad1858 use an input pin to control the mode configuration of the input data port. mode (pin 3) programs the input data port mode as follows: figure 9 shows the ad1857 left-justified mode. l r clk is hi for the left channel, and lo for the right channel. data is valid on the rising edge of bclk. the msb is left-justified to an l r clk transition, with no msb delay. the left-justified mode can be used in the 16-, 18- or 20-bit input mode. mode (pin 3) ad1857 serial input port mode lo left-justified (see figure 9) hi i 2 s-justified (see figure 10) mode (pin 3) ad1858 serial input port mode lo right-justified (see figure 11) hi left-justified dsp serial port style (see figure 12) figure 10 shows the ad1857 i 2 s-justified mode. l r clk is lo for the left channel, and hi for the right channel. data is valid on the rising edge of bclk. the msb is left-justified to an l r clk transition, but with a single bclk period delay. the i 2 s-justified mode can be used in the 16-, 18- or 20-bit input mode. figure 11 shows the ad1858 the right-justified mode. l r clk is hi for the left channel, and lo for the right channel. data is valid on the rising edge of bclk. the msb is delayed 16-bit clock periods from an l r clk transition so that when there are 64 bclk periods per l r clk period, the lsb of the data will be right-justified to the next l r clk transition. left channel right channel bclk input sdata input lrclk input msb msb-1 msb-2 lsb+2 lsb+1 lsb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb figure 9. ad1857 left-justified mode lrclk input bclk input sdata input left channel right channel msb msb-1 msb-2 lsb+2 lsb+1 lsb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb figure 10. ad1857 i 2 s-justified mode left channel right channel bclk input sdata input lrclk input msb msb-1 msb-2 lsb+2 lsb+1 lsb msb-1 msb-2 lsb+2 lsb+1 lsb msb lsb figure 11. ad1858 right-justified mode
ad1857/ad1858 rev. 0 C11C left channel right channel bclk input sdata input lrclk input msb msb-1 lsb+2 lsb+1 lsb msb-1 lsb+2 lsb+1 lsb msb msb-1 msb figure 12. ad1858 left-justified dsp serial port style left channel right channel bclk input sdata input lrclk input msb msb-1 lsb+2 lsb+1 lsb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 lsb msb-2 msb figure 13. ad1857/ad1858 32 3 f s packed mode figure 12 shows the ad1858 left-justified dsp serial port style mode. l r clk must pulse hi for at least one bit clock period before the msb of the left channel is valid, and l r clk must pulse hi again for at least one bit clock period before the msb of the right channel is valid. data is valid on the falling edge of bclk. note that in this mode, it is the responsibility of the dsp to ensure that the left data is transmitted with the first l r clk pulse, the right data is transmitted with the second l r clk pu lse, and synchronism is maintained from that point forward. note that in 16-bit input mode, the ad1857/ad1858 are capable of a 32 f s bclk frequency packed mode where the msb is left-justified to an l r clk transition, and the lsb is right-justified to an l r clk transition. l r clk is hi for the left channel, and lo for the right channel. data is valid on the rising edge of bclk. packed mode can be used when the ad1857 is programmed in left-justified mode, or when the ad1858 is programmed in right-justified mode. packed mode is shown in figure 13. master clock the synchronous master clock of the ad1857/ad1858 is supplied by an external clock source applied to mclk. figure 14 shows example connections. do not change the state of the 384/ 256 pin while the ad1857/ad1858 is operational; this pin should be hardwired lo or hi. alternatively, its state may be changed while the pd / rst pin is asserted lo. 1 mclk 6 256 mode 384 mode sample rate 12.288mhz 18.432mhz 48khz 44.1khz 32khz 11.2896mhz 16.9344mhz 8.192mhz 12.288mhz 384/ 256 mclk frequency 384/ 256 = lo 384/ 256 = hi figure 14. ad1857/ad1858 clock connections digital mute the ad1857/ad1858 offer a control pin that mutes the analog output. by asserting the mute (pin 15) signal hi, both the left channel and the right channel are muted. the ad1857/ ad1858 have been designed to minimize pops and clicks when muting and unmuting the device. the ad1857/ad1858 include a zero crossing detector which attempts to implement mute on waveform zero crossings only. if a zero crossing is not found within 1024 input sample periods (approximately 23 milliseconds at 44.1 khz), the output is muted regardless. output drive, buffering and loading the ad1857/ad1858 analog output stage is able to drive a 2 k w load. if lower impedance loads must be driven, an external buffer stage such as the analog devices ssm2142 should be used. the analog output is generally ac coupled with a 10 m f capacitor as shown in figure 21. it is possible to dc couple the ad1857/ad1858 output into an op amp stage using the cmout signal as a bias point. on-chip voltage reference the ad1857/ad1858 include an on-chip voltage reference that establishes the output voltage range. the nominal value of this reference is +2.25 v, which corresponds to a line output voltage swing of 3 v p-p. the line output signal is centered around a voltage established by the cmout (common-mode output) (pin 10). the reference must be bypassed both on the filt input (pin 11) with 10 m f and 0.1 m f capacitors, and on the cmout output (pin 10) with 10 m f and 0.1 m f capacitors, as shown in figure 21. both the filt pin and the cmout pin use the agnd ground. the on-chip voltage reference may be overdriven with an external reference source by applying this voltage to the filt pin. cmout and filt must still be bypassed as shown in figure 21. an external reference can be useful to calibrate multiple ad1857/ad1858 dacs to the same gain. reference bypass capacitors larger than those suggested can be used to improve the signal-to-noise performance of the ad1857/ad1858. power-down and reset the pd / rst input (pin 2) is used to control the power consumed by the ad1857/ad1858. when pd / rst is held lo, the ad1857/ad1858 are placed in a low dissipation power-down state. when pd / rst is brought hi, the ad1857/ad1858 become ready for normal operation. the master clock (mclk, pin 1) must be running for a successful reset or power-down operation to occur. the pd / rst signal must be lo for a minimum of four master clock periods (326 ns with a 12.288 mhz mclk frequency). when the pd / rst input (pin 2) is brought hi, the ad1857/ ad1858 are reset. all registers in the ad1857/ad1858 digital engine (serial data port, interpolation filter and modulator) are zeroed, and the amplifiers in the analog section are shorted during the reset operation. the ad1857/ad1858 have been designed to minimize pops and clicks when entering and exiting the power-down state.
ad1857/ad1858 rev. 0 C12C figure 18 shows the suggested interface to the philips saa2500* mpeg audio decoder ic. the saa2500 supports 18 bits of data using an i 2 s-compatible output format. sck ws fsclkin sd saa2500 256 x f s hi l r clk bclk sdata mode ad1857 384/ 256 20 19 18 3 6 mclk 1 hi figure 18. interface to saa2500 figure 19 shows the suggested interface to the zoran zr38000* dsp chip, which can act as an mpeg audio or ac-3 audio decoder. the zr38000 supports 16 bits of data using a left- justified output format. 20 sckb wsb sckin sdb zr38000 256 x f s lo l r clk bclk sdata mode ad1857 384/ 256 19 18 3 6 mclk 1 hi figure 19. interface to zr38000 figure 20 shows the suggested interface to the c-cube microsystems cl480* mpeg system decoder ic. the cl480 supports 16 bits of data using a right-justified output format. 20 19 18 da-bck da-lrck da-xck da-data cl480 256 x f s hi l r clk bclk sdata mode ad1858 3 6 384/ 256 hi mclk 1 figure 20. interface to cl480 control signals the mode and deemp control inputs are normally connected hi or lo to establish the operating state of the ad1857/ad1858. they can be changed dynamically (and asynchronously to the l r clk and the master clock) as long as they are stable before the first serial data input bit (i.e., the msb) is presented to the ad1857/ad1858. application issues interface to mpeg audio decoders figure 15 shows the suggested interface to the analog devices adsp-21xx family of dsp chips, for which several mpeg audio decode algorithms are available. the adsp-21xx supports 16 bits of data using a left-justified dsp serial port style format. sclk dr rfs tfs dt adsp-21xx nc nc hi l r clk bclk sdata mode ad1858 384/ 256 19 18 20 3 6 nc = no connect hi mclk 1 figure 15. interface to adsp-21xx figure 16 shows the suggested interface to the texas instruments tms320av110* mpeg audio decoder ic. the tms320av110 supports 18 bits of data using a right-justified output format. sclk lrclk pcmclk pcmdata tms320av110 256 x f s hi l r clk bclk sdata mode ad1858 384/ 256 18 19 20 3 6 mclk 1 hi figure 16. interface to tms320av110 figure 17 shows the suggested interface to the lsi logic l64111* mpeg audio decoder ic. the l64111 supports 16 bits of data using a left-justified output format. sclko lrclko sysclk sero l64111 384 x f s lo l r clk bclk sdata mode ad1857 384/ 256 20 19 18 3 6 mclk 1 lo figure 17. interface to l64111 *all trademarks are properties of their respective holders.
ad1857/ad1858 rev. 0 C13C 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 digital ground plane mclk dv dd sdata l r clk bclk pd / rst mode nc av dd mute dgnd deemp 384/ 256 av dd outl agnd cmout filt agnd outr analog ground plane nc = no connect ferrite bead figure 22. recommended ground plane layout and decoupling considerations the recommended decoupling, bypass and output circuits for the ad1857/ad1858 are shown in figure 21. pcb and ground plane recommendations the ad1857/ad1858 ideally should be located above a split ground plane, with the digital pins over the digital ground plane and the analog pins over the analog ground plane. the split should occur between pins 6 and 7, and between pins 14 and 15 as shown in figure 22. the ground planes should be linked with a ferrite bead. this ground plane strategy maximizes the ad1857/ad1858s analog audio performance. 2.2 m f right line output left line output av dd agnd filt cmout +5v analog sdata blck l r clk mode agnd dv dd dgnd +5v digital outl outr mute deemp nc pd / rst bias voltage for external use +5v analog av dd nc = no connect 0.1 m f 4.7 m f 0.1 m f 4.7 m f ad1857/ad1858 mclk 256 mode 384 mode sample rate 12.288mhz 18.432mhz 48khz 44.1khz 32khz 11.2896mhz 16.9344mhz 8.192mhz 12.288mhz 384/ 256 mclk frequency 384/ 256 = lo 384/ 256 = hi dsp or audio decoder 0.1 m f 2.2 m f m controller 4.7 m f 0.01 m f 12 11 8 13 10 9 7 14 1 6 18 19 3 20 16 2 15 5 4 17 4.7 m f right line output left line output outl outr 2.2 m f 8 13 100k 820pf 1k w + 2.2 m f 100k 820pf 1k w + *optional output filter * * figure 21. recommended circuit connection
ad1857/ad1858 rev. 0 C14C bclk l r clk sdata left-justified mode ad1857 sdata right-justified mode ad1858 lsb sdata i 2 s-justified mode ad1857 t dbh t dbp t dbl t dls t dds msb msb-1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb figure 23. serial data port timing bclk l r clk sdata left-justified dsp serial port style mode ad1858 msb-1 t dbh t dbp t dbl t dls t dlh t dds t ddh msb figure 24. serial data port timingCdsp serial port style mode (ad1858 only) pd / rst mclk t pdrp figure 25. power-down/reset timing timing diagrams the serial data port timing is shown in figures 23 and 24. the minimum bit clock hi pulse width is t dbh and the minimum bit clock lo pulse width is t dbl . the minimum bit clock period is t dbp . the left/ right clock minimum setup time is t dls and the left/ right clock minimum hold time is t dlh . the serial data minimum setup time is t dds and the minimum serial data hold time is t ddh . the power-down/reset timing is shown in figure 25. the minimum reset lo pulse width is t pdrp (four mclk periods) to accomplish a successful ad1857/ad1858 reset operation.
ad1857/ad1858 rev. 0 C15C outline dimensions dimensions shown in inches and (mm). 20-lead ssop (rs-20) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements
c2218C12C4/97 printed in u.s.a. C16C

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